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Ordering number : ENA1650A
CMOS IC
LC72715PW
Overview
Mobile FM Multiplex Broadcast IC with On-Chip VICS Decoder
The LC72715PW is a data demodulation LSI for receiving FM multiplex broadcasts for mobile reception in the DARC format. This LSI includes an on-chip bandpass filter for extracting the DARC signal from the FM baseband signal. It also integrates a decoder that performs the VICS data processing on the same chip and can implement a compact, multifunction VICS reception system. LC72715PW is control-compatible with LC72714W and LC72710LW. (Description of dGPS reception function has been deleted, because the dGPS service finished at the end of March 2008). Note that a contract with the VICS Center is required to evaluate this LSI's sample and to produce VICS compatible products. It also requires a contract with the NHK Engineering Service to produce VICS compatible products.
Functions
* Adjustment-free 76kHz SCF bandpass filter * Built-in VICS decoder * MSK delay detection system based on a 1T delay. * Error correction function based on a 2T delay (in the MSK detection stage) * Digital PLL based clock regeneration function * Shift-register 1T and 2T delay circuits * Block and frame synchronization detection circuits * Functions for setting the number of allowable BIC errors and the number of synchronization protection operations. * Error correction using (272, 190) codes * Built-in layer 4 CRC code checking circuit * On-chip frame memory and memory control circuit for vertical correction * 7.2MHz crystal oscillator circuit * Two power saving modes: STNBY and EC STOP * Applications can use either a parallel CPU interface (DMA) or a CCB serial interface. * Supply voltage: 2.7V to 3.6V
* *
CCB is a registered trademark of SANYO Semiconductor Co., Ltd. CCB is SANYO Semiconductor's original bus format. All bus addresses are managed by SANYO Semiconductor for this format.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
D1510HKIM 20101126-S00003/N1010HKIM 20100119-S00005 No.A1650-1/26
LC72715PW
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0V
Parameter Maximum supply voltage Input voltage Symbol VDD VIN1 A0/CL, A1/CE, A2/DI, RST, STNBY (VDD is equal to 2.7V or more.) A0/CL, A1/CE, A2/DI, RST, STNBY (VDD is less than 2.7V.) VIN2 Output voltage Output current VOUT IOUT1 IOUT2 Allowable output current (total) Allowable power dissipation Operating temperature Storage temperature ITTL Pd max Topr Tstg Ta85C Input pin other than VIN1 Output pin INT, RDY, DREQ, D0 to D15, D O Output pin other than IOUT1 Total for all the output pins Conditions Ratings -0.3 to +4.0 -0.3 to +5.6 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 0 to 2.0 0 to 1.0 10 200 -40 to +85 -55 to +125 Unit V V V V V mA mA mA mW C C
Allowable Operating Ranges at Ta = -40C to +85C, VSS = 0V
Parameter Supply voltage Input high-level voltage Symbol VDD VIH1 VIH2 A0/CL, A1/CE, A2/DI, RST, STNBY IOCNT1, IOCNT2, DACK D0, D1, D2, D3, D4, D5, D6, D7 WR, RD, A3, CS VIH3 Input low-level voltage VIL1 VIL2 SP, BUSWD, TIN, TPC1, TPC2, TOSEL1, TOSEL2 A0/CL, A1/CE, A2/DI, RST, STNBY IOCNT1, IOCNT2, DACK D0, D1, D2, D3, D4, D5, D6, D7 WR, RD, A3, CS VIL3 Oscillation frequency XIN input sensitivity Input amplitude FOSC VXI VMPX1 SP, BUSWD, TIN, TPC1, TPC2, TOSEL1, TOSEL2 XIN, XOUT XIN MPXIN SCF Oscillation circuit Within 250ppm Capacitive coupling 100% demodulation composite VDD=3.3V VMPX2 MPXIN SCF 100% demodulation composite VDD=2.7V 120 450 mVrms 120 500 mVrms 400 0.0 7.2 0.3VDD V MHz mVrms Schmitt 0.0 0.3VDD V Schmitt 0.7VDD 0.0 VDD 0.3VDD V V Schmitt 0.7VDD VDD V Schmitt Pin Name Type Conditions min 2.7 0.7VDD Ratings typ max 3.6 5.5 V V unit
No.A1650-2/26
LC72715PW
Electrical Characteristics at Ta = -40C to +85C, VDD = 2.7V to 3.6V, VSS = 0V
Parameter Input high-level current Symbol IIH1 IIH2 Pin Name A0/CL, A1/CE, A2/DI, RST, STNBY IOCNT1, IOCNT2, DACK D0, D1, D2, D3, D4, D5, D6, D7 WR, RD, A3, CS IIH3 Input low-level current IIL1 IIL2 SP, BUSWD, TIN, TPC1, TPC2, TOSEL1, TOSEL2 A0/CL, A1/CE, A2/DI, RST, STNBY IOCNT1, IOCNT2, DACK D0, D1, D2, D3, D4, D5, D6, D7 WR, RD, A3, CS IIL3 Output high-level voltage VOH1 VOH2 SP, BUSWD, TIN, TPC1, TPC2, TOSEL1, TOSEL2 CLK16, DATA, FLOCK, BLOCK, FCK, BCK, CRC4 DREQ, RDY, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, INT Output low-level voltage VOL1 VOL2 CLK16, DATA, FLOCK, BLOCK, FCK, BCK, CRC4 DREQ, RDY, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, INT VOL3 Output leakage current Hysteresis voltage IOFF VHYS
DO DO
Type Schmitt Schmitt
Conditions min
Ratings typ max 1.0 1.0
unit A A
1.0 Schmitt Schmitt -1.0 -1.0
A A A
-1.0 CMOS CMOS IOH=-2mA CMOS CMOS IOL=2mA Nch-Open Drain 0.4 VDD-0.4 IOH=-1mA VDD-0.4
A V
V
IOL=1mA
0.4
V
V
IOL=2mA VO=VDD
0.4 1.0
V A
A0/CL, A1/CE, A2/DI, RST, STNBY, IOCNT1, IOCNT2, DACK D0, D1, D2, D3, D4, D5, D6, D7 WR, RD, A3, CS 0.1VDD V
Internal feedback resistance Current drain
RF IDD
XIN, XOUT
1.0 6 12
M mA
Bandpass Filter Characteristics at Ta = 25C, VDD = 2.7V to 3.6V, VSS = 0V
Parameter Input resistance Reference supply voltage output BPF center frequency -3dB band width Group-delay in band width Gain Attenuation characteristic Symbol RMPX VREF FC FBW DGD Gain ATT1 ATT2 ATT3 ATT4 Conditions min MPXIN-Vssa, f=100kHz Vref, Vdda=3V FLOUT FLOUT FLOUT FLOUT-MPXIN, f=76kHz FLOUT, f=50kHz FLOUT, f=100kHz FLOUT, f=30kHz FLOUT, f=150kHz 25 15 50 50 20 Ratings typ 50 1.5 76.0 19.0 7.5 max k V kHz kHz s dB dB dB dB dB unit
No.A1650-3/26
LC72715PW
Block Diagram
BUSWD SP RST STNBY CS A3 A2/DI A1/CE A0/CL RD WR DO Frame memory Error correction and Layer 2 CRC CCB IF Output control and CPU register Parallel IF
Vssa Vref MPXIN Vdda FLOUT CIN Vref + -
Reference voltage Antialiasing filter 76kHz BPF(SCF) Timing control
Vssd Vddd INT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 No.A1650-4/26
PN demodulation
VICS processing
Internal clock 2T Delay Divider 1T Delay Vssd XIN
LPF
MSK correction circuit Clock regeneration Layer 4 CRC
Synchronization regeneration
LPF
XOUT Vddd IOCNT1 IOCNT2
FLOCK BLOCK FCK BCK
CLK16 DATA
Package Dimensions
unit : mm (typ) 3190A
12.0 48 49 33 32
0.5
10.0
64 1 0.5 (1.25)
(1.5)
17 16 0.18 0.15
1.7max
0.1
SANYO : SQFP64(10X10)
10.0
12.0
CRC4 DREQ DACK Vssd Vddd RDY
LC72715PW
Pin Assignment
BUSWD
STNBY
A1/CE
A0/CL
A2/DI
Vddd 34
Vssd
RST
WR
48
47
46
45
44
43
42
41
40
39
38
37
36
35
33
INT
DO
RD
NC
CS
SP
A3
TIN NC Vssa Vref MPXIN Vdda FLOUT CIN NC TPC1 TPC2 TEST TOSEL1 TOSEL2 Vssd XIN
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9
32 31 30 29 28 27 26
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LC72715PW
25 24 23 22 21 20 19 18 17
IOCNT1
IOCNT2
XOUT
FLOCK
DATA
FCK
CRC4
BLOCK
DREQ
DACK
Vddd
CLK16
Vddd
Vssd
RDY
BCK
Top view
List of Pin Functions
Pin No. 1 2 3 Name of Pin XOUT Vddd IOCNT1 IO Form O I State with RST="L" Oscillation Input Description of Functions Pin for system clock (crystal oscillator) Digital power pin Data bus I/O control 1 input pin (Parallel IF) * Connect to Vssd when CCB IF (SP=H) is to be used. Data bus I/O control 2 input pin (Parallel IF) * Connect to Vssd when CCB IF (SP=H) is to be used. Clock regeneration monitor pin Demodulation data monitor pin Frame synchronization flag output pin (H: synchronized) Block synchronization flag output pin (H: synchronized) Frame start signal output pin Block start signal output pin Layer 4 CRC check result output pin DMA REQ signal output pin (parallel IF) DMA ACK signal input pin (parallel IF) * Connect to Vddd when CCB IF (SP=H) is to be used. Digital GND pin Digital power pin Read data READY signal output pin (parallel IF)
4 5 6 7 8 9 10 11 12 13 14 15 16
IOCNT2 CLK16 DATA FLOCK BLOCK FCK BCK CRC4 DREQ DACK Vssd Vddd RDY
I O O O O O O O O I O
Input L L L L L L H H Input H
Continued on next page.
No.A1650-5/26
LC72715PW
Continued from preceding page.
Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name of Pin D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 INT Vddd Vssd
DO
IO Form I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O I I I I I I I I I I I I AO AI AO AI I I I I I I
State with RST="L" Input Input Input Input Input Input Input Input Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z H Hi-Z(H) Input Input Input Input Input Input Input Input Input Input Input Input Vdda/2 Input Vdda/2 Input Input Input Input Input Input Oscillation
Description of Functions Data bus 0 to 7 I/O pins (parallel IF) Bus width switched to 8 bits or 16 bits according to the BUSWD setting * Connect to Vssd when CCB IF (SP=H) is to be used.
Data bus 8 to 15 output pins (parallel IF) * Output OFF for 8 bit bus width (BUSWD=L)
Interrupt output pin for external CPU Digital power pin Digital GND pin
D O output pin (CCB IF)
NC WR RD A0/CL A1/CE A2/DI A3 CS STNBY RST SP BUSWD TIN NC Vssa Vref MPXIN Vdda FLOUT CIN NC TPC1 TPC2 TEST TOSEL1 TOSEL2 Vssd XIN
NC pin (This pin must be open.) Write control signal input pin (parallel IF) * Connect to Vddd when CCB IF (SP=H) is to be used. Read control signal input pin (parallel IF) * Connect to Vddd when CCB IF (SP=H) is to be used. CL input pin (CCB IF)/ address input pin 0 (parallel IF) CE input pin (CCB IF)/ address input pin 1 (parallel IF) DI input pin (CCB IF)/ address input pin 2 (parallel IF) Address input pin 3 (parallel IF) * Connect to Vssd when CCB IF (SP=H) is to be used. Chip selector input pin (parallel IF) * Connect to Vddd when CCB IF (SP=H) is to be used. Standby mode input pin (H: standby) System reset input pin (L: reset) CCB/parallel setting input pin (H: CCB, L: parallel) Data bus width setting input pin (L: 8 bits, H: 16 bits) Test input pin (This pin must be connected to Vssd.) NC pin (This pin must be open.) Analog GND pin Reference voltage output pin (Vdda/2) Baseband (multiplex) signal input pin Analog power pin Subcarrier output pin (76kHz BPF output) Subcarrier input pin (comparator input) NC pin (This pin must be open.) Test input pin (This pin must be connected to Vssd.) Test input pin (This pin must be connected to Vssd.) Test mode setting pin (This pin must be connected to Vssd.) Test input pin (This pin must be connected to Vssd.) Test input pin (This pin must be connected to Vssd.) Digital GND pin System clock pin (crystal oscillator/external clock input)
No.A1650-6/26
LC72715PW
Internal Equivalent Circuit of Analog Pins
Name of pin Pin number in parentheses Internal equivalent circuit
MPXIN(53)
+
FLOUT(55)
-
+
CIN(56)
Vref
Vdda
Vref(52)
Vssa
No.A1650-7/26
LC72715PW
CPU Interface
CCB (Computer Control Bus), which is the Sanyo original serial bus format for Sanyo's acoustic LSIs, performs data input and output. The CCB address is transmitted with CE= "L", acknowledging the CCB I/O mode when CE is set to "H". (1) List of CCB modes
CCB address Hexadecimal FAh FBh FCh FDh B0 0 1 0 1 B1 1 1 0 0 B2 0 0 1 1 B3 1 1 1 1 A0 1 1 1 1 A1 1 1 1 1 A2 1 1 1 1 A3 1 1 1 1 I/O mode Input Output Input Output Description 16-bit control data input Output of data corresponding to the input clock (CL) portion Layer 4 CRC check circuit data input (on the 8-bit units) Output of the register only
(2) Data input (CCB address FAh) This is to set data to the LSI internal register. DI input includes both CCB address FAh and 16-bit data (DI0 to DI15) are input. Assignment of each bit is as shown in the table below. Though DI12 to DI15 are invalid data, it is necessary to enter the arbitrary data so that the total of 16 bits can be obtained. For the contents of each register and register address, refer to the chapter of CPU registers. (Note that writing into the layer 4 CRC check register will be described later (for the CCB address, use FCh.))
(LSB) DI0 BIT0 DI1 BIT1 DI2 BIT2 DI3 BIT3 Input data (8-bit) DI4 BIT4 DI5 BIT5 DI6 BIT6 (MSB) DI7 BIT7 DI8 BIT0 Register address DI9 BIT1 DI10 BIT2 DI11 BIT3 Invalid data DI12 to DI15 BIT4 to BIT7
tEL CE tCH CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 tCL
tES
tEH
DI0
DI1 Internal data latch
DI13
DI14
DI15 tLC
(3) Output of the corrected data (CCB address FBh) The corrected packet data is output from LSI. The CCB address, FBh, is input in DI. The valid data to be output is maximum 288 bits. If the clock input (CL input) is interrupted halfway to set CE to the "L" level, data output is not troubled by the next interrupt. The maximum data to be output is 288 bits (36 bytes) and the leading two bytes, to which the status register (STAT) contents and the block number register (BLNO) contents are added, are output. STAT and BLNO, which are the register contents outputs, are output respectively with LSB first. The corrected data is output sequentially beginning with the leading bit in data of one block. The BIC code is not output. In case of data reading for multiple times by one interrupt signal (INT), the output data is not guaranteed.
STAT (8)
D O 0 to D O 7
BLN0 (8)
D O 8 to D O 15
Data block (176)
D O 16
Error-corrected data to
D O 191
Layer 2 CRC (14)
D O 192 to D O 205
Parity (82)
D O 206 to D O 287
No.A1650-8/26
LC72715PW
tEL CE tCH CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 tDDO DO DO0 DO1 DO2 DO285 DO286 DO287 tDDO2 tCL tEH tES
(4) Layer 4 CRC check circuit (CCB address FCh) This is a function to detect the error in the data group (Layer 4 CRC), transmitting the data group of specified number of bytes, via the CCB interface, to LSI. The CCB address is FCh. In this case, it is not necessary to send register address. The length of data group to be transmitted is on the 8-bit units. Here is not any upper limit (such as N pieces in the figure below) for the length of data to be transmitted at a time and data transmission can be divided into multiple times.
tEL CE tCH CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 CR0 CR1 N-3 N-2 N-1 tCRC CRC4 pin output Note: The number of Ns must be on the 8-bit units. Output after transmission of N pieces tCL tEH tES
(5) Register output (CCB address FDh) This is the dedicated register that can read only the status register (STAT) and block number register (BLNO) in LSI. To DI, the CCB address (FDh) is input. Data is output in order of the status register and the block number register.
tEL CE tCH CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 tDDO DO ST0 ST1 ST2 BLN5 BLN6 BLN7 tDDO2 tCL tEH tES
No.A1650-9/26
LC72715PW
Symbol tCL tCH tSU tHD tEL tES tEH tLC
tDD O *1 tDDO 2
Parameter Clock "L" level time Clock "H" level time Data setup time Data hold time CE wait time CE setup time CE hold time Data latch change time
D O data output time D O data output off time
min 0.7 0.7 0.7 0.7 0.7 0.7 0.7
typ
max
unit s s s s s s s s ns ns
0.7 277 140 0.7 555
tCRC
CRC4 change period
s
*1 DO data output change time from the "H" level to the "L" level. Output change time from the "L" level to the "H" level is determined by the external pull-up resistance value and load capacitance value.
CPU Interface
This LSI can perform control via the parallel interface, in addition to the CCB interface. To use the parallel interface, it is necessary to set the SP pin = L. The data bus width can be selected with the BUSWD pin. (BUSWD pin - L: 8 bits, H: 16 bits) The DMA transmission method can also be selected according to the setting of control register. (1) Data input (register setting) Data is set to the register in LSI. For accessing, input the register address to A0 to A3 pins and the write data to the D(n) pin. Set the CS pin = L, and then the WR pin = L. Subsequently, by setting the WR pin = H and the CS pin = H after the tWWRL period, the data can be set to the register. It is necessary to keep an interval of tCYWR or more before the next data input.
tSAWR A0 to A3 tWWRL tHAWR
CS tCYWR
WR tWDS D(n) tWDH
No.A1650-10/26
LC72715PW
(2) Register output This is to read data from the register in LSI. Only the status register (STAT) and block number register (BLNO) in LSI can be read. For accessing, input the register address in A0 to A3, set the CS pin = L, and then the RD pin = L. This causes the RDY pin to change from "H" to "L". Then, data is output from the D(n) pin after the RDY pin becomes "H". It is necessary to keep an interval of tCYRD or more before the next data output. (n: 0-7 for BUSWD=L and 0 - 15 for BUSWD=H.) By setting bit 3 (RDY) = 1 of the control register 2, the RDY pin output method can be changed. In this case, the RDY pin changes from "H" to "L" in the timing enabling output of the acquired data and the pin returns to "H" after the end of data output (shown as Timing 2 in the figure).
tWRDL
tSARD A0 to A3
tHARD
CS tCYRD
RD tDRDY RDY (Timing1: default) tDRDY+tWRDY RDY (Timing2) tRDH D(n) tDATON VALID OUTPUT tDDATn tDRDY2 tWRDY
No.A1650-11/26
LC72715PW
(3) Corrected data output This is to output the packet data after correction processing from LSI. The total length of output data is 176 bits (22 Bytes) only, and the Layer 2 CRC data (14 bits) and parity data (82 bits) are not output. The corrected data is output, on either the 8-bit or 16-bit units, sequentially from the leading data among those in one packet. The BIC code is not output. The accessing method is the same as for the register output and the address "0" is input to A0 to A3 pins. Since this is different from the register output in the timing conditions during access, the timing chart is shown here separately from the register output. The RDY signal output method can also be selected similarly.
Data block (176 bits) Data after error correction Layer 2 CRC (14 bits) Parity (82 bits)
Structure of a Single Data Packet (Total length 272 bits: BIC not included)
tWDRD tSARD A0 to A3 tHARD
CS tCYRD
RD tDRDY RDY (Timing1: default) tDRDY+tWRDY RDY (Timing2) tRDH D(n) tDATON VALID OUTPUT tDDATn VALID OUTPUT * A0 to A3 should be set to 0 during reading of corrected data. tDRDY2 tWDRDY
(4) Layer 4 CRC check output This is a function to detect error of data group (layer 4 CRC). The CRC4 pin = "H" or bit1 (CRC4) = 1 of the status register after writing of the data group into the layer 4 CRC register means that there is no error. The accessing method is the same as for the data input, and the address "6h" of the layer 4 CRC register is input into the register address. (5) DMA transmission output Setting bit0 (DMA) = 1 of control register 2 causes the DMA mode, allowing the corrected data to be output in the DMA method. For accessing, input the address "0h" to A0 to A3 pins after falling of the DREQ output pin, setting the CS pin = L, and then the RD pin = L. After the DREQ pin = H, data is acquired from the D(n) pin. Then, the wait state occurs for the tCYDM period or longer till the DREQ pin becomes "L". In the DMA mode, only 8 bits can be selected for the data bus width. (n: 0 to 7 for BUSWD=L. Do not set BUSWD=H because it may cause fault.) The DACK pin can be used instead of the RD pin for DMA transmission. In this case, it is necessary to set bit1 (DMA_RD) = 1 of the control register 2. It is also possible to change the polarity of DREQ and DACK pins. In this case, it is necessary to set bit4 (DREQ) = 1 and bit5 (DACK) = 1 of the control register 2.
No.A1650-12/26
LC72715PW
tRDDM DREQ tDREQ tCYDM
DACK (when DACK is selected) tWRDM RD (default)
A0 to A3
0 tSARD
0 tHARD
CS tRDH D(n) tDDATn *A0 to A3 should be set to 0 during DMA transmission VALID OUTPUT VALID OUTPUT
Symbol tSARD tHARD *1 tWRDL tCYRD tWRDY tRDH tSAWR tHAWR tCYWR tWWRL tWDS tWDH tDRDY tDRDY2 tWDRD Address and CS to RD setup RD to address and CS hold RD "L" level width RD cycle wait RDY width (at register output) RD data hold Address and CS to WR setup WR to address and CS hold WR cycle wait WR "L" level width WR data setup WR data hold RDY output delay RDY output delay 2
Parameter
min 20 0 340 150 60 0 20 20 150 200 20 20 0 0 340 620 60 300 20
typ
max
unit ns ns ns ns
210 40
ns ns ns ns ns ns ns ns
40 40
ns ns ns ns
RD width at output of corrected data BUSWD=L (8bit) RD width at output of corrected data BUSWD=H (16bit)
tWDRDY
RDY width at output of corrected data BUSWD=L (8bit) RDY width at output of corrected data BUSWD=H (16bit)
210 490
ns ns ns
tRDDM tDREQ tDATON tDDATn tCYDM tWRDM
DMA start time DACK to DREQ delay DATn output start time DATn output delay DMA cycle wait RD "L" level width at DMA transmission output
260 0 0 40 40 420 300
ns ns ns ns ns
*1 Specified up to the earliest negating of A0 to A3 and CS
No.A1650-13/26
LC72715PW
CPU Registers
This LSI has both write registers and read registers. Access to the registers is made via CCB IF or parallel IF. Switching of access mode is made with the SP pin. (CCB IF: SP=H, Parallel IF: SP=L) (1) Write registers Setting any data to `0h' or `7h' or larger address of Write-registers is prohibited. Do not set any data to these addresses. * List of write registers
ADR 0h 1h 2h 3h 4h 5h 6h 7h and beyond R/W W W W W W W Register Name BIC SYNCB SYNCF CTL1 CTL2 CRC4 Reserved (setting prohibited) Allowable number of BIC errors Block synchronization: error protection count Frame synchronization: error protection count Control register 1 Control register 2 Layer 4 CRC register (for the parallel IF only. CCB to use the dedicated address) Reserved (setting prohibited) Description
* 1h : Number of allowable BIC errors Register to set the allowable number of BIC error bits for determination of synchronization
ADR 1h Register Name BIC Bit 7-4 3-0 Name BIC_B BIC_F Description Backward protection value (initial value 2) Sets the number of allowable BIC error bits (when not synchronized). Forward protection value (initial value 2) Sets the allowable number of BIC error bits (when synchronized). Reset 0010b 0010b
When the block synchronization determination output (BLOCK) is to be used determination of whether or not there is any FM multiplex data, it is recommended to set the allowable number of BIC errors during backward protection to `0001b' or `0000b'.
No.A1650-14/26
LC72715PW
* 2h : Block synchronization: error protection count Register to set the number of block synchronization protections for determination of block synchronization.
ADR 2h Register Name SYNCB Bit 7-4 3-0 Name SYNCB_B SYNCB_F Description Backward protection value (Register initial value 1: Number of backward protections 2) Number of backward protections = Backward protection value +1 Forward protection value (Register initial value 7: Number of forward protections 8) Number of forward protections = Forward protection value +1 Reset 0001b 0111b
To change the set value, it is necessary to set the value determined by deducting 1 from the desired number of protections. The number of forward and backward protections can be set separately. The conditions for counting the number of protections are as follows: * Number of backward protections (not synchronized): BLOCK=L) When the timing of the free-run counter for LSI internal synchronization agrees with that of received BIC, the protection counter is incremented by 1. Similarly, when the timing between the LSI internal counter and the received BIC is lost, the protection counter is cleared to zero. The count timing is the timing of the LSI internal counter. * Number of forward protections (synchronized: BLOCK=H) Contrarily to the case of backward protection, the number of protections is counted up when the timing of LSI internal free-run counter is deviated from the received BIC detection timing. The number of protections is cleared to zero when they agree. The figure below shows the agreement/disagreement between the LSI internal timing and received BIC timing and the relationship between the protection counter value and BLOCK signal. For the number of forward/backward protections of 3, the protection counter value at a timing of BLOCK signal changeover is 2, that is, smaller by 1. The number of protections is determined in the internal circuit by comparing the register set value for the number of forward/backward protections and the protection counter. Accordingly, the register set value must be set to the value smaller than the desired number of protections by 1. For example, when the number of both forward and backward protections is 3 as shown below, it is necessary to set `22h'. If the set value is `00h', the number of protections becomes 1 by definition for forward and backward protections. However, the operation becomes the same as for the state without the protection circuit. When the block synchronization flag output (BLOCK) is to be used for determination whether or not there is FM multiplex data, it is recommended to reset the value severer than the initial value.
BIC Received data BIC position of synchronization counter Protection counter BLOCK 0 1 2 0 1 2 3 Reset
1 1
2 2
3 0 1 0
For the register set value of 22h: the number of both the forward and backward protections become 3.
* 3h : Frame synchronization: error protection count Register to set the number of frame synchronization protections for determination of frame synchronization
ADR 3h Register Name SYNCF Bit 7-4 Name SYNCF_B Backward protection value (Register initial value 1: Number of backward protections 2) Number of backward protections = Backward protection value +1 3-0 SYNCF_F Forward protection value (Register initial value 7: Number of forward protections 8) Number of forward protections = Forward protection value +1 0111b 0001b Description Reset
To change the set value, it is necessary to set the value determined by deducting 1 from the desired number of protections. This LSI detects BIC peculiar change points exist at four points in one frame and increases/decreases the counts of protection counter by determining agreement/disagreement with the timing counter for LSI internal frame synchronization.
No.A1650-15/26
LC72715PW
* 4h : Control register 1 Register to control the block reset ON/OFF, function activation/stop, and the data output method.
ADR 4h Register Name CTL1 Bit 7 Name CRC4_RST Description Layer 4 CRC check circuit reset setting 1: Reset ON 6
D O _MOVE
Reset
0: Reset OFF
0
To cancel reset, it is necessary to set 0. Sets the D O pin output method changeover 0: Hi-Z state retained in states other than data output 1: Changes in an interlocked manner with the INT signal 5 INT_MOVE Sets changeover of corrected data output method *4 0: Outputs only data received at completion of correction & layer 2 CRC completion as well as during synchronization 1: Outputs all of data 4 SYNC_RST Synchronization regeneration circuit reset setting *1 1: Reset ON 3 EC_STOP 0: Reset OFF 0 0 to be set to cancel reset Error correction function down setting *2 0: All functions activated 1: Only MSK detector circuit and synchronization regeneration circuit activated 2 VEC_HALT Vertical error correction function down function *3 0: Executes vertical error correction and second horizontal correction. 1: Does not execute vertical error correction and second horizontal correction. 1 0 Reserved Reserved 0 0 0 0 0 0
*1 With SYNC_RST=1, the synchronization status and the synchronization protection status are cleared, resulting in the unsynchronized state. This function enables rapid pull-in of frame synchronization when the frame synchronization of new tuned and received data is deviated during tuning of a radio receiver. In this case, registers such as the number of allowable BIC errors, the number of block forward/backward protections, and the number of frame forward/backward protections are not initialized. During reset, the INT signal is not output and the DO pin becomes the HI-Z output. *2 With EC_STOP=1, all of operations and data output related to error correction is shut down. MSK demodulation, synchronization circuits, serial data input, and layer 4 CRC circuit remain operative. *3 With VEC_HALT=1 setting, all of LSI operation related to vertical correction and second horizontal correction are shut down. Only the data after first horizontal correction is output. *4 Since the output mode will be modified depending on the setting of the VEC_OUT flag or the result of horizontal error correction, refer to the "List of operation modes" section for detail.
No.A1650-16/26
LC72715PW
* 5h : Control register 2 Register to control the parallel IF setting, vertically-corrected data output method, etc.
ADR 5h Register Name CTL2 Bit 7 6 Name Reserved BLK_RST Description Either keep an initial value or set it to 0. Block synchronization circuit reset setting *1 1: Reset ON 5 DACK 0: Reset OFF 0 0 to be set to cancel reset DACK signal polarity setting (effective for SP=L only) 0: Negative logic for DACK signal polarity 1: Positive logic for DACK signal polarity 4 DREQ DREQ signal polarity setting (effective for SP=L only) 0: Negative logic for DREQ signal polarity 1: Positive logic for DREQ signal polarity 3 RDY RDY signal timing setting (effective for SP=L only) 0: Outputs the RDY signal in the timing 1. 1: Outputs the RDY signal in the timing 2. 2 VEC_OUT Vertically error corrected data output method changeover setting *2 0: No vertically error corrected output if vertical error correction has not been made 1: All data output even when vertical error correction has not been made 1 DMA_RD DMA read control signal selection setting (effective for SP=L only) 0: RD signal used 1: DACK signal used 0 DMA DMA transmission function enable setting (effective for SP=L only) 0: DMA transmission not used for reading of corrected data 1: DMA transmission used for reading of corrected data 0 0 0 0 0 0 Reset 0
*1 With BLK_RST=1, the block synchronization state and block synchronization protection counter value are cleared. But this does not affect the functions related to frame synchronization. *2 With VEC_OUT=1, one frame of data completely free from error. The data similar to the horizontally-corrected data is output in the timing of output of vertically-corrected data even when vertical correction has not been made. * 6h : Layer 4 CRC register Register for data group writing to check the layer 4 CRC. Used on with the parallel IF. The dedicated CCB address is to be used for CCB IF.
ADR 6h Register Name CRC4 Bit 7 6 5 4 3 2 1 0 Name CRCDAT7 CRCDAT6 CRCDAT5 CRCDAT4 CRCDAT3 CRCDAT2 CRCDAT1 CRCDAT0 Layer 4 CRC check data setting By writing value consecutively into this register, the layer 4 CRC check of data group comprising multiple bytes can be made. The CRC checked results can be known by checking the CRC4 flag in the status register or CRC4 pin output. Description Reset 0 0 0 0 0 0 0 0
No.A1650-17/26
LC72715PW
(2) Read registers * List of read registers
ADR 0h 1h 2h 3h and beyond R/W R R R Register Name PDATO STAT BLNO Description Input this address into A0 to A3 after reading of error-corrected data Status register Block number register Reserved
Parallel mode: To read registers, send address shown in the list of read registers. CCB mode: To read registers, send assigned CCB address (FBh or FDh). It is not necessary to send address shown in the list of read registers. * 1h : Status register Register to confirm various states
ADR 1h Register Name STAT Bit 7 Name VH Description Determination on vertically error corrected data 0: Data for which only horizontal correction is performed 1: Data for which vertical and second horizontal correction after horizontal correction are performed 6 BLK Block synchronization state 0: Data that is received when block synchronization is not established 1: Data that is received when block synchronization is established 5 FRM Frame synchronization state 0: Data that is received when frame synchronization is not established 1: Data that is received when frame synchronization is established 4 ERR Error correction state 0: Data whose correction is completed and for which error is not detected by the layer 2 CRC check 1: Data whose correction is impossible or for which error is detected by the layer 2 CRC check. 3 PRI Determination of parity block 0: Data that is estimated to be data block by the frame synchronization circuit 1: Data that is estimated to be parity block by the frame synchronization circuit 2 HEAD Frame head determination 1: Data that is estimated to be the frame head block by the frame synchronization circuit 0: Data other than above 1 CRC4 Layer 4 CRC check result 0: Error in layer 4 CRC check result 1: No error in layer 4 CRC check result 0 Reserved 0 1 0 0 0 0 0 0 Reset
* 2h : Block Number register Register to confirm the output data block Number
ADR 2h Register Name BLNO Bit 7 6 5 4 3 2 1 0 Name BLN7 BLN6 BLN5 BLN4 BLN3 BLN2 BLN1 BLN0 Data block Number Parity block Number 0 to 189 0 to 81 Description Indicates the block Number or parity block Number of output data Reset 0 0 0 0 0 0 0 0
No.A1650-18/26
LC72715PW
* Data renewal timing of read register The timing for rewriting of read register (STAT, BLNO) data is 1ms up to a time point immediately before changing of INT from H to L. * Read procedure of corrected data Normally, the status register is first read because of occurrence of interrupt to check the condition of corrected output data that is output by the interrupt signal, determining whether or not read is necessary. For example, read is not made till the next interrupt if the error correction result is NG and read is not necessary. For CCB IF, data read is made at the CCB address, `FBh', and determination is made by means of the status information added by 16 bits to see if the subsequent data is to be read. When interrupting read, set the CE signal to "L". It is possible to read the register in a manner asynchronous with the interrupt signal. For example, to check the current receiving state, read the status register to check BLK (data received during block synchronization) and FRM (data received during frame synchronization). In this case, read data is more close to the current receiving state, when VH=0 (data subject to horizontal correction only) information is used. * Layer 4 CRC check To perform layer 4 CRC check, the data group to be checked is transmitted. After transmission, it is determined that the data group is free from error if the CRC4 pin becomes the H-level output or the status register CRC4 (layer 4 CRC check result) is `1'. The CRC4 pin or CRC4 flag of status register is either "H" or "1" when all bits of check register in LSI are "0". To perform layer 4 CRC check using this function, it is necessary to initialize the CRC check register in LSI before transmission of one group of one data group. Initialization is made by setting the CRC4_RST (layer 4 CRC check circuit reset) of control register to `1'. Subsequently, to transmit the layer 4 CRC check data, set CRC4_RST back to 0 to cancel reset. The generating polynomial of CRC code is as follows: G(X) = X16 + X12 + X5 + 1
No.A1650-19/26
LC72715PW
Error Correction
(1) Error Correction and Output Conditions of Error-corrected Data (in the default state) The received data is subject to error detection by the layer 2 CRC and error correction by the (272,190) code for each one block (272 bits). At the end of correction, preparation for transmission to CPU is made and the INT signal is output. This is called "horizontal correction". In the default state, this INT signal is output only when the output data concerned meets all of three conditions as follows: Data whose error correction is completed and for which layer 2 CRC detects no error Data received during block and frame synchronizations Data in the data packet *Depending on the register mode setting, horizontally-corrected data may be output regardless of conditions of above.
to
When horizontal correction cannot cover completely, correction by the product code is made frame by frame. For data that cannot be horizontally corrected, the second horizontal correction is made. This series of operations is called "vertical correction". Conditions for the data obtained from vertically-corrected output are as follows in the default state: Data that cannot be corrected by horizontal correction, but that has been completely corrected by the vertical correction Data in the data packet Accordingly, horizontally-corrected data is not output. Packet data that cannot be corrected horizontally or vertically is not output. The parity packet data after vertical correction is not output either. Vertical correction is applied to the whole packet data that have been received during frame synchronization, and is executed when horizontal correction cannot correct all packet (block) data. Vertical correction is not made when the error-free data is received for one frame or when the received data is not in flame synchronization during reception. For the packet whose error has been corrected by horizontal correction and any error-free packet, vertical correction is not made to prevent faulty correction. In the default setting, the applicable vertically-corrected output is not output when vertical correction has not been made. * Depending on the register mode setting, the vertically-corrected data may be output regardless of whether or not vertical correction is to be made.
No.A1650-20/26
LC72715PW
(2) Error-corrected Data Output Timing (Basic Restrictions) Data received by LSI is corrected error and written sequentially without any interruption into the output data buffer memory. Since this data buffer memory has a capacity for one-block data, the corrected data before reading is overwritten by the next data if data read is delayed. In consequence, it is essential to read data according to the timing stipulations shown below. This LSI specifies the output timing for each of horizontally and vertically corrected data as follows: Upon completion of preparation for the output data, LSI lowers the INT pin to "L" as a request for transmission. Data output has the period during which only horizontal data can be read and the period during which horizontal and vertical data are read according to the time division. Complete data transmission within about 9ms after INT = "L". When only the horizontally-corrected data can be output, data transmission is possible for about 18ms. Even when CPU is in the course of reading, the output buffer is overwritten by the next output data once the specified time period is expired. The data amount that can be read by one horizontal and vertical transmission request (INT) is one block only. Vertically-corrected data is output sequentially beginning with the first block after completion of vertical correction, but the data of parity block is not output.
Output of only horizontal data INT 1ms
18ms
Horizontal data output period Divided output for horizontal and vertical data INT 1ms Horizontal data output period Vertical data output period 68s 68s
9ms
Period during which data guarantee is impossible
No.A1650-21/26
LC72715PW
(3) Horizontally-corrected Data Output Timing (Relationship With The Received Data) The timing relationship between the received data and interrupt control signal (INT) for horizontary-corrected data output is shown. But the delay from the actual received signal caused by demodulation in the MSK demodulation block is ignored. Block synchronization is established by determining the BIC code. Data of the Nth packet can be output during receiving of the next (N + 1) packet data.
(N-1) packet Received data BIC 18ms 300ns max BCK 300ns max INT 1ms (N-1) packet data output period N packet data output period 68s Period during which data cannot be guaranteed 62.5s N packet BIC (N+1) packet
(4) Vertically-corrected Data Output Timing Vertical correction is made when the data of one frame is stored in the memory, frame synchronization has been established, and when horizontal correction cannot correct all of packet data. Vertical correction start timing is the head of a frame. During receiving of the first to 28th packets of the N-th frame, horizontal correction of each packet is made, transferring data to the CPU interface. Using the idling time in this period, vertical correction of the previous (N-1)-th frame data is made. Vertically-corrected data is output for the amount equivalent to 190 blocks sequentially beginning with reception of the 29th packet (block), in such a manner that one block data is output each time one block is received. Only data of data block in the FM multiplex broadcasting frame is output. The final 190th block is output during reception of the 218th block. In the vertically-corrected data output timing, the packet data corrected by horizontal correction is not output (INT not issued). However, vertical correction data output order is not shortened for the amount equivalent to the packet data that is not output. For example, if the first to 100th data packets have been horizontally corrected, the 101st vertically corrected packet data is output, not at the reception point of the block Number 29 th, but at the 129th packet data reception point.
(N-1)-th frame Reception block No. BCK 271 272 1 2 3 28
N-th frame 29 30 31 218 219 220
FCK
62.5s 18ms 1 2 189 190
INT 1ms 18ms 18msx28=504ms 9ms 9ms Data output period after vertical correction of previous frame
No.A1650-22/26
LC72715PW
(5) List of Operation Modes Depending on the set value of INT_MOVE (bit 5 of control register 1) and VEC_OUT (bit 2 of control register 2), the INT signal output timing and output data are modified. In the table below, indicates "output", x indicates "no output." and - indicates "none applicable."
Horizontal Parameter INT_MOVE VEC_OUT correction result Default value 0 0 OK NG Mode 1 1 1 OK NG Mode 2 1 0 OK NG Mode 3 0 1 OK NG x x x Horizontally-corrected output OK data NG data x Parity x x Vertically-corrected output OK data x *1 *2 *2 x *3 *4 NG data x -
*1 Only data whose horizontal correction result is NG and whose vertical correction result is OK is output. *2 All of vertically-corrected outputs (190 blocks/frame) are output, in both cases of horizontal correction result of OK and NG, regardless of whether the vertical correction result is OK or NG. *3 The vertically-corrected data is not output when there is no data that is determined to be NG because all the horizontal correction results are OK. *4 When there is any data whose horizontal correction result becomes NG, all of vertically-corrected outputs (190 blocks/frame) are output regardless of whether the vertical correction result is OK or NG.
No.A1650-23/26
LC72715PW
Application Sample Circuit Diagram
This is an application circuit example when the CCB serial interface is selected, using a microcomputer operating on the supply voltage of 3V. The DO pin must be pulled up by a resistor to the supply voltage.
CPU Interface
5k
Analog GND 3.3F 10F 330pF FM composite 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TIN NC Vssa Vref MPXIN Vdda FLOUT CIN NC TPC1 TPC2 TEST TOSEL1 TOSEL2 Vssd XIN
BUSWD SP RST STNBY CS A3 A2/DI A1/CE A0/CL RD WR NC DO Vssd Vddd INT
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
LC72715PW
560pF 22H 22H
Xtal 7.2MHz 22pF 22pF
Crystal oscillator 7.200MHz SMD-49 made by DAISHINKU CORP.
The capacitance value to be connected to the above crystal oscillator is the reference value. Before use, confirm that oscillation is free from trouble using the actual substrate.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
XOUT Vddd IOCNT1 IOCNT2 CLK16 DATA FLOCK BLOCK FCK BCK CRC4 DREQ DACK Vssd Vddd RDY
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
0.01F 100F
VDD
GND
No.A1650-24/26
LC72715PW
Cautions
Operation at Reset and Standby (1) Reset signal Reset operation is performed by setting the RST pin input level to VIL or less for 300ns or more at the supply voltage (VDD) of 2.5V or more. (See the figure below). Be sure to perform reset operation at power ON.
2.5V Supply Voltage VIH RST 300ns(min) VIL(0.3VDD)
(2) Pin state at reset Refer to the list of pin functions. (3) Reset operation range The reset signal causes reset inside LSI, causing return to the initial state. Though the crystal oscillation circuit is not stopped, the internal divider circuit is stopped. (4) Data input after reset If 300ns or more time has elapsed after completion of reset, the register write control circuit is ready for activation. (5) Standby mode Set the STNBY pin to the "H" level, and LSI enters the standby mode. In this mode, all of LSI operations can be stopped. After canceling of STNBY, the time is required till the crystal oscillation circuit becomes stable. Digital pin output states during standby is the same as for that during reset. On the other hand, analog output pins (FLOUT, Vref) are L outputs (Vdda/2 is output during reset). Similarly to the case of reset, the LSI inside is reset to return to the initial state.
No.A1650-25/26
LC72715PW
* The DARC (Data Radio Channel) FM multiplex broadcast technology was developed
by NHK (Japan Broadcasting Corporation). * The DARC is a registered trademark of NHK Engineering Services,Inc. (NHK-ES). * A separate contract with NHK-ES is required in advance for the manufacture and/or sales of electronic equipment in Japan and other countries that uses the patents, which are related to DARC technology, and which are registered in Japan and such other countries by NHK independently or in cooperation with a third party. * DARC and the logo shown on the right-hand side can be displayed on electronic equipment that uses DARC technology by the conclusion of a contract with NHK-ES.
Please contact NHK Engineering Services for further details. Contact information: NHK Engineering Services,Inc. Phone: +81- (0)3-5494-2400 (main) URL: http://www.nes.or.jp/index.html *Note The number of shipments of this LSI will be reported to NHK-ES by SANYO Semiconductor Co., Ltd (the number of samples is excluded).
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of December, 2010. Specifications and information herein are subject to change without notice.
PS No.A1650-26/26

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